

module rasterizer(clock, address_b, clock_b, data_b, wren_b, q_b, back_buffer, using_buffer);
	input wire clock;
	output reg [15:0] address_b;
	output wire clock_b;
	output wire [3:0] data_b;
	output wire wren_b;
	input wire [3:0] q_b;
	input wire back_buffer;
	output reg using_buffer;
	
	
	assign wren_b = 1;
	assign clock_b = clock;
	assign data_b = 4'b1111;
	
	always @* begin
		if(back_buffer)begin 
			address_b <= 6666 + 200*150;
			using_buffer <= 0;
		end
		else begin
			address_b <= 6666;
			using_buffer <= 0;
		end
	end
endmodule








